DANG Nam Khanh
- Department of Computer Science and Engineering/Division of Computer Science
- Associate Professor
- Courses - Undergraduate
- Courses - Graduate
Electron device and electronic equipment
- Neuromorphic Computing
- Machine Learning
- Educational Background, Biography
- Ph.D. in Computer Science and Engineering, The University of Aizu, Japan, 2017
- M.Sc. in Information Systems & Technology, University of Paris-XI, France, 2014
- B.Sc. in Electronics & Telecommunications, VNU University of Engineering and Technology, Vietnam, 2011
- Associate Professor, The University of Aizu, 2022 April - now.
- Assistant Professor, VNU University of Engineering and Technology, Vietnam National University, Hanoi, 2017 November - 2022 March.
- Visiting Researcher, The University of Aizu, 2020 November - 2021 March.
- Visiting Researcher, The University of Aizu, 2019 May - 2019 September.
- Researcher, SISLAB, Vietnam National University, Hanoi, 2011-2014.
- RTL Designer, Dolphin Vietnam Inc., 2010-2011.
- Current Research Theme
- Key Topic
- Neuromorphic Computing, Faul-tolerance, VLSI, 3D Integrated Circuits
- Affiliated Academic Society
- 3D Spiking Neuromorphic Processor
Neuromorphic computing uses Spiking Neuron Network models to solve machine learning problems in a more power/energy-efficient way when compared to the conventional Artificial Neural Networks.
This project aims to research and develop an adaptive low-power spiking neural network system in hardware (NASH) empowered with our earlier developed fault-tolerant three-dimensional on-chip interconnect technology. The NASH system features the following: (1) An efficient adaptive configuration method to enable the reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.), (2) A mixture of different deep NN topologies, (3) An efficient fault-tolerant multicast spike routing algorithm, (4) An efficient on-chip learning mechanism.
To demonstrate the performance of the NASH system, an FPGA implementation shall be developed, and a VLSI implementation shall also be established.
- Advanced Interconnect Technologies for Network-on-Chips (2D, 3D, Si-Photonics, Hybrid)
Complex SoCs contain dozens of components made of processor cores, DSPs, memory, accelerators, and I/O, all integrated into a single die area of just a few square millimeters. Such complex systems will be interconnected via a complex on-chip interconnect closer to a sophisticated network than current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low. Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, and low-latency adaptive routing.
- AIzuHand: Adaptive Real-time Non-invasive Neuromorphic Neuroprosthesis Hand
Restoring grasping and movement for people with amputations and neurological impairment is imperative for retrieving independence. Prosthetic limbs, which are becoming widespread therapeutic solutions can significantly restore grasping and improve the quality of life of people with amputations or neurological disabilities. However, unlike living agents that combine different sensory inputs to perform a complex task accurately, most prostheses use uni-sensory input, offer limited degrees of freedom and need long patient training.
We investigate adaptive prosthetic limbs to restore grasping and sensation for persons with amputation and neurological impairments. In particular, we develop non-invasive technologies directly interfacing the environment with the residual arm or legs.
Dissertation and Published Works
- A. Ben Abdallah, Khanh N. Dang, Masayuki Hisada, “TSV Error Tolerant Router Device for 3D Network On Chip”, 特許第7239099号, Japan patent.
- Ngo-Doanh Nguyen, Xuan-Tu Tran, Abderazek Ben Abdallah, Khanh N. Dang, “An In-situ Dynamic Quantization with 3D Stacking Synaptic Memory for Power-aware Neuromorphic Architecture”, IEEE Access, vol. 11, pp. 82377-82389, 2023.
- Khanh N. Dang, Nguyen Anh Vu Doan, Abderazek Ben Abdallah “MigSpike: A Migration Based Algorithm and Architecture for Scalable Robust Neuromorphic Systems”, IEEE Transactions on Emerging Topics in Computing (TETC), [DOI: 10.1109/TETC.2021.3136028].
- Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran, “HotCluster: A thermal-aware defect recovery method for Through-Silicon-Vias Towards Reliable 3-D ICs systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, Volume 41, No. 4, pp. 799-812, April 2022. [DOI: 10.1109/TCAD.2021.3069370].
- Khanh N. Dang, Akram Ben Ahmed, Ben Abdallah Abderrazak and Xuan-Tu Tran, “TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE, Volume 28, Issue 3, pp. 672 - 685, 2020. [DOI: 10.1109/TVLSI.2019.2948878].
- Khanh N. Dang, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, “Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, Volume 8, Issue 3, pp. 577-590, 2020. [DOI: 10.1109/TETC.2017.2762407].
- Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, “A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE, Volume 25, Issue 11, pp. 3099-3112, 2017. [DOI: 10.1109/TVLSI.2017.2736004].
More details: https://u-aizu.ac.jp/~khanh/