Welcome! ようこそ！
My name is Khanh N. Dang (in Vietnamese: Đặng Nam Khánh, in Japanese: ダン ナム カイン).
I am currently an Associate Professor in the Division of Computer Engineering, Department of Computer Science and Engineering, The University of Aizu. I received my Ph.D. from the University of
Aizu and my M.Sc. from Paris-Sud University (now is Paris-Saclay University). Before joining the University of Aizu’s faculty, I was an assistant professor at Vietnam National University, Hanoi. I also worked at Dolphin-IC in the past.
Research Interests: My research spans 3D VLSI design, thermal-awareness, near-threshold computing and neuromorphic computing. In particular, I have a strong interest in building on the 3D Integrated Circuit based neuromorphic computing architecture that is ultra-low-power and scalable enough to be safely and responsibly deployed in the real world.
Email: khanh@u-aizu.ac.jp | Contact: Contact Info
» For prospective GT undergraduate and graduate students, research topics (VLSI design, approximate computing, or neuromorphic computing) are available; interested potential candidates please email me.
News
- 2024-01: Our paper on using Spiking Neural Networks to predict and control multi-core systems has been accepted for Microprocessors and Microsystems. The source code is opened here.
- 2023-12: Our genetic algorithm framework for mapping neuromorphic systems (with multi-chip/fault-tolerance awareness) is now open-sourced. Please access it at https://github.com/klab-aizu/HeterGenMap.
- 2023-09: Our paper titled “Power-aware Neuromorphic Architecture with Partial Voltage Scaling 3D Stacking Synaptic Memory” has been accepted for IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
- 2022-07: Our book titled “Neuromorphic Computing Principles and Organization” is now available on Springer (URL), Amazon (URL) and Amazon-JP (URL).
- 2022-04: I joined the University of Aizu as an associate professor in April of 2022. Visit my Univ. of Aizu Profile here!
- 2022-01: Our paper titled “A Low-Power, High-Accuracy with Fully On-Chip Ternary Weight Hardware Architecture for Deep Spiking Neural Networks” has been accepted for Microprocessors and Microsystems.
- 2021-11: Our paper titled “MigSpike: A Migration Based Algorithm and Architecture for Scalable Robust Neuromorphic Systems” has been accepted for IEEE Transactions on Emerging Topics in Computing (TETC).
- 2021-03: Our paper titled “HotCluster: A thermal-aware defect recovery method for Through-Silicon-Vias Towards Reliable 3-D ICs systems” was accepted for publication in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
- 2020-08: Our paper “Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems” was published for IEEE Transactions on Emerging Topics in Computing (TETC).
- 2020-04: Our paper titled “TSV-OCT: A scalable online multiple TSV defects localization for 3D-ICs” was published for IEEE Trans. on VLSI systems!
- 2019-04: We visited Prof. Pham’s Laboratory at UC Davis as a part of our WorldBank-funded project.
- 2018-12: Our project had been funded by NAFOSTED under No. 102.01-2018.312 (2019 - 2021).