Research

Three-Dimensional (3D) Integrated Circuits

As Moore’s Law is reaching its limitation of transistor’s size, one of the approach is to extend vertically by stacking multiple layers of silicon on top of each others and connect them using inter-layer vias. Here, we focus on designing 3D architecture such as stacking memories (SRAM, eDRAM, etc …) and converting the normal 2D architectures to 3D ones.

Neuromorphic Computing

Inspired by the structure and function of the human brain, we design neuromorphic computers/chips consisting of physical artificial neurons (made from silicon) to do computations of a mimic version of biological brains. Here, we focus on digital approach in combination with 3D Integrated Circuits and Network-on-Chip. Our system is designed on both hardware (Verilog HDL) and software model (Python).

Machine Learning/Optimization for Computer-Aided Design

We target to solve complicated problem of Computer-Aided Design using machine learning and optimization technique. Despite being decided by the designers, we aim to develop the platform to generate the design. Our main focus is using Genetic Algorithm/Reinforcement Learning on thermal awareness and reliability.

Undervolted/Near-Threshold Computing

Beside conventional computing, lowering the operating voltage to near the threshold can help significantly reduce the power consumption. However, lowering the operating voltage make the system more vulnerable to noise. In this research topic, we investigate on the impact of lowering the voltage on chip design and how to handle the noise.

Approximate Computing

To reduce the power consumption and area cost, one of the approaches is to deloy approximate circuits. Here, instead of giving the exact results, we design a circuit to provide so-called ‘‘good enough’’ results.

Fault-tolerant Computing

Devices after manufacture and during wareout can suffer permanent defects that affect the accuracy of the device. Another type of fault is transient one when alpha particles or noises cause fluctuations in the cells/transistor causing incorrect consequence. In this topic, we research on how to predict and tolerate the potential faults.

Grant

'’Low-power Spiking Neural Network Solution for IoT and Edge devices’‘, main PI, funded by UoA Competitive Research Funding under No. P26-2023 (2023-2024).
“Hotspot aware Fault-Tolerant Architectures and Algorithms for TSV-based 3D Network-on-Chips”, main PI, funded by National Foundation for Science and Technology Development (NAFOSTED) under No. 102.01-2018.312 (2019-2021).
“Soft Error Resilient Architecture and Algorithm for Network-on-Chip” : main PI, funded by VNU University of Engineering and Technology (VNU-UET) under project No. CN18.10 (2018-2019).
“Development of IoT Dual Band Transmitters for Agriculture (IOTA)”, core member, funded by the Ministry of Science and Technology (World Bank project) (2018-2019).
“Reconfiguration Solution in Designing Network-on-Chip Architectures “, core member, funded by National Foundation for Science and Technology Development (NAFOSTED) under No. 102.01-2013.17 (2014-2016).
“Investigation, Design, and Implementation of a Video Encoder for Next Generation Multimedia Equipment”, core member, funded by Vietnam National University, Hanoi (VNU) under No. QGĐA.10.02 (2010-2013).

Award

Second Prize (the 2nd best) of Vietnamese Nhan Tai Dat Viet Award 2015. The Second Prize awarded to our VENGME H.264/AVC encoding chip which I took part in the design team.
Best Student Paper Award at International Symposium on Ubiquitous Networking (UNet 2021) for paper: Ogbodo Mark Ikechukwu, Khanh N. Dang and Abderazek Ben. Abdallah, ‘‘Energy-efficient Spike-based Scalable Architecture for Next-generation Cognitive AI Computing Systems’’. [Certificate]
Best Paper Award at 2023 IEEE 6th International Conference on Electronics Technology (ICET) for the paper: Jiangkun Wang, Khanh N. Dang and Abderazek Ben Abdallah, ‘‘Scaling Deep-Learning Pneumonia Detection Inference on a Reconfigurable Self-Contained Hardware Platform’’.