Research
Research Topics
Three-Dimensional (3D) Integrated Circuits
With Moore’s Law reaching limitations in transistor scaling, one solution is to expand vertically by stacking multiple silicon layers interconnected by vias. Our focus is on designing 3D architectures, such as memory stacks (SRAM, eDRAM, etc.), and converting conventional 2D architectures to 3D.
Power-Efficient Generative AI
As next-generation AI models demand significant power, our research addresses this with advanced VLSI techniques like approximation, near-threshold computing, and data compression.
Neuromorphic Computing
Inspired by the human brain, we design neuromorphic chips featuring physical artificial neurons made of silicon. These chips perform computations that mimic biological brain functions. Our approach combines digital methods with 3D Integrated Circuits and Network-on-Chip (NoC) structures, developed in both hardware (Verilog HDL) and software (Python) models.
Machine Learning/Optimization for Computer-Aided Design
We tackle complex Computer-Aided Design (CAD) challenges using machine learning and optimization techniques. Our goal is to create platforms capable of generating optimized designs, focusing on thermal awareness and reliability using Genetic Algorithms and Reinforcement Learning.
Undervolted/Near-Threshold Computing
Lowering operating voltage to near-threshold levels can drastically reduce power consumption. However, this also increases susceptibility to noise. We investigate the impact of undervolting on chip design and develop strategies to manage noise.
Approximate Computing
To reduce power and area costs, we deploy approximate circuits that deliver “good enough” results rather than exact outcomes, optimizing for efficiency.
Fault-Tolerant Computing
Devices can experience permanent defects over time, affecting performance accuracy. Additionally, transient faults, caused by alpha particles or noise, can lead to incorrect results. We research methods to predict and tolerate these potential faults.
Current and Previous Projects
Details of our ongoing and completed projects can be found here.
Grants
- “Combination of Approximate Computing and Approximate Stacking Memory for Low-Power Neuromorphic Computing”, Principal Investigator, funded by UoA Competitive Research Funding, No. P24-2024 (2024-2025).
- “Low-Power Spiking Neural Network Solution for IoT and Edge Devices”, Principal Investigator, funded by UoA Competitive Research Funding, No. P26-2023 (2023-2024).
- “Hotspot-Aware Fault-Tolerant Architectures and Algorithms for TSV-Based 3D Network-on-Chips”, Principal Investigator, funded by National Foundation for Science and Technology Development (NAFOSTED), No. 102.01-2018.312 (2019-2021).
- “Soft Error Resilient Architecture and Algorithm for Network-on-Chip”, Principal Investigator, funded by VNU University of Engineering and Technology (VNU-UET), No. CN18.10 (2018-2019).
- “Development of IoT Dual-Band Transmitters for Agriculture (IOTA)”, Core Member, funded by the Ministry of Science and Technology (World Bank Project) (2018-2019).
- “Reconfiguration Solutions in Network-on-Chip Architectures”, Core Member, funded by NAFOSTED, No. 102.01-2013.17 (2014-2016).
- “Investigation, Design, and Implementation of a Video Encoder for Next-Generation Multimedia Equipment”, Core Member, funded by Vietnam National University, Hanoi (VNU), No. QGĐA.10.02 (2010-2013).
Awards
- Second Prize in the Vietnamese Nhan Tai Dat Viet Award 2015. Awarded for our VENGME H.264/AVC encoding chip, for which I was part of the design team.
- Best Student Paper Award at the International Symposium on Ubiquitous Networking (UNet 2021) for the paper:
- Ogbodo Mark Ikechukwu, Khanh N. Dang, and Abderazek Ben. Abdallah, “Energy-Efficient Spike-Based Scalable Architecture for Next-Generation Cognitive AI Computing Systems”. Certificate
- Best Paper Award at the 2023 IEEE 6th International Conference on Electronics Technology (ICET) for the paper:
- Jiangkun Wang, Khanh N. Dang, and Abderazek Ben Abdallah, “Scaling Deep-Learning Pneumonia Detection Inference on a Reconfigurable Self-Contained Hardware Platform”.
Collaborators
(in alphabetical order)
- Akram Ben Ahmed, National Institute of Advanced Industrial Science and Technology (AIST), Japan
- Nguyen Anh Vu Doan, Infineon Technologies AG, Germany
- Michael Meyer, Eastern Washington University, USA
- Xuan-Tu Tran, Vietnam National University, Hanoi, Vietnam