齋藤 寛

SAITO Hiroshi

Professor, Head of the Computer Engineering Division

Affiliation
Department of Computer Science and Engineering/Division of Computer Engineering
Title
Professor, Head of the Computer Engineering Division
E-Mail
hiroshis@u-aizu.ac.jp
Web site
https://www-adl.u-aizu.ac.jp/en/

Education

Courses - Undergraduate
Logic Circuit Design, Advanced Logic Circuit Design, Integrated Exercise for Systems I
Courses - Graduate
Electronic Design Automation for System-level Design, Design Automation for Digital VLSIs

Research

Specialization
Design automation of asynchronous circuits, design of edge AI devices, development of wild animal alert systems
Educational Background, Biography
1998 Bachelor, The University of Aizu 2000 Master, The University of Aizu 2003 Ph.D, The University of Tokyo 2003 - 2004 Research Assistant, The University of Tokyo 2004 - 2007 Assistant Professor, The University of Aizu 2007 - 2012 Associate Professor, The University of Aizu 2012 - 2021 Senior Associate Professor, The University of Aizu
Current Research Theme
The same as Specialization""
Key Topic
非同期式回路、FPGA、エッジAI
Affiliated Academic Society
IEEE, ACM, IEICE, IPSJ

Others

Hobbies
School days' Dream
Current Dream
Motto
Favorite Books
Messages for Students
Publications other than one's areas of specialization

Dissertation and Published Works

1. Hideki Katabami, Hiroshi Saito, Tomohiro Yoneda, "Design of a GALS-NoC using Soft-cores on FPGAs" Proc. 2013 IEEE 7th International Symposium on Embedded Multicore Mancore System-on-Chip (MCSoC), pp.31-36, September 2013.
2. Minoru Iizuka and Hiroshi Saito, "A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation" Proc. 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), pp.1-4, June 2013.
3. Minoru Iizuka, Naohiro Hamada, and Hiroshi Saito, "An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation"IEICE Transactions on Electronics, Volume E96-C No.4, pp.482?491, April 2013.
4. Hiroshi Saito, Tomohiro Yoneda, and Yuichi Nakamura, "An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip", Proc. IEEE International Symposium on Embedded Multicore SoCs, Septermber 2012.
5. Naohiro Hamada and Hiroshi Saito, "Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation", IEICE Transaction, Volume E95-C No.4, pp.506?515, April 2012.
6. Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, and Minoru Yoshinaga, "A Tool Set for the Design of Asynchronous Circuits with Bundled-data Implementation", International Conference on Computer Design 2011,pp.78?83, October 2011.
7. Naohiro Hamada and Hiroshi Saito, "Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-data Implementation", GLS VLSI'11 VLSI,pp.157?162, May 2011.
8. Hiroshi Saito and Naohiro Hamada, "A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs", International Symposium on Circuits and Systems (ISCAS 2010),pp.925?928, May 2010.
9. Naohiro Hamada, Yuuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Cris Myers, and Takashi Nanya, "A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation", IPSJ Transaction on System LSI Design Methodology, no.2, pp.67?79, Feburary 2009.