Pipelined Datapath and Control

Objective: In this lab exercise, you will use schematic design and Verilog design to implement the pipelined datapath and control in FIGURE 6.30 (see the figure) in the text book (the index of the figure might be different if you use an old version of the book). 

Pipelined Datapath and Control Specification: Read Section 6.2 of A Pipelined Datapath and Section 6.3 of Pipelined Control in the text book. The implementation of pipelined datapath and control (see the figure) covers the MIPS instruction subset, including load word (lw), store word (sw), branch equal (beq), the arthmetic-logical instructions add, sub, and, or, and set on less than (slt) and immediate instructions (addi, andi, ori,slti). In this design, the division of an instruction into five stages means a five-stage pipeline, which in turn means that up to five instructions will be in execution during any single clock.

1. Main control unit: Since pipelining the datapath leaves the meaning of the control lines unchanged, we can use the same control values in the single-cycle CPU.

Table 1: Truth table of the main control function for the pipelined CPU

Input or output	Signal name	R-format	lw	sw	beq	addi	andi	ori	set less than immediate
Inputs	Op5	0	1	1	0	0	0	0	0
	Op4	0	0	0	0	0	0	0	0
	Op3	0	0	1	0	1	1	1	1
	Op2	0	0	0	1	0	1	1	0
	Op1	0	1	1	0	0	0	0	1
	Op0	0	1	1	0	0	0	1	0
Outputs	RegDst	1	0	x	x	0	0	0	0
	ALUSrc	0	1	1	0	1	1	1	1
	MemtoReg	0	1	x	x	0	0	0	0
	RegWrite	1	1	0	0	1	1	1	1
	MemRead	0	1	0	0	0	0	0	0
	MemWrite	0	0	1	0	0	0	0	0
	Branch	0	0	0	1	0	0	0	0
	ALUOp1	1	0	0	0	1	1	1	1
	ALUOp0	0	0	0	1	1	1	1	1

The nine control lines can be grouped by pipeline stages:

• Execution/Address Calculation stage control lines.

 

Instruction	RegDst	ALUOp1	ALUOp0	ALUSrc
R-format	1	1	0	0
lw	0	0	0	1
sw	x	0	0	1
beq	x	0	1	0
Immediate	0	1	1	1

• Memory access stage control lines

 

Instruction	Branch	MemRead	MemWrite
R-format	0	0	0
lw	0	1	0
sw	0	0	1
beq	1	0	0
Immediate	0	0	0

• Write-back stage control lines

 

Instruction	RegWrite	MemtoReg
R-format	1	0
lw	1	1
sw	0	x
beq	0	x
Immediate	1	0

Since the control lines start with the EX stage, we can create the control information during instruction decode (ID stage). Figure 1 shows that these control signals are used in the appropriate pipeline stage as the instruction moves down the pipeline. Figure 2 shows the full datapath with the pipeline registers and with the control lines connected to the proper stage.
 

2.  ALU control unit: The following table is a copy from ALU control bits in the single-cycle CPU designed in Lab 4. Pipelined CPU uses the same ALU control bits in the single-cycle CPU.

Table 2: ALU control bits

Instruction opcode	ALUOp	Instruction operation	opcode	Function field	Desired ALU Action	ALUcontrol input
LW	00	load word	xxxxxx	xxxxxx	add	010
SW	00	store word	xxxxxx	xxxxxx	add	010
Branch equal	01	branch equal	xxxxxx	xxxxxx	subtract	110
R-type	10	add	xxxxxx	100000	add	010
R-type	10	subtract	xxxxxx	100010	subtract	110
R-type	10	AND	xxxxxx	100100	and	000
R-type	10	OR	xxxxxx	100101	or	001
R-type	10	set less than	xxxxxx	101010	set less than	111
Immediate	11	addi	001000	xxxxxx	add	010
Immediate	11	andi	001100	xxxxxx	and	000
Immediate	11	ori	001101	xxxxxx	or	001
Immediate	11	set less than immediate	001010	xxxxxx	set less than	111

Lab Requirements:

1. to build the pipelined datapath and control from the single-cycle datapath and control. The major elements are exactly the same as those in the single-cycle datapath and control. The only elements you need to add are IF/ID pipeline register, ID/EX pipeline register, EX/MEM pipeline register, and MEM/WB pipeline register. Kepp design of IF/ID pipeline register, ID/EX pipeline register, EX/MEM register, MEM/WB register, and PC (program counter) in the same method, that is, use Verilog or Schematic, but do not mix up Verilog and Schematic in the design of the register. Hint of design of pipelined datapath:
• copy the schematic of the single-cycle datapath to the schematic of the pipelined datapath.
• delete all the connections in the schematic.
• add pipeline registers. Be clear how many bits each pipeline register contain.
• add connection lines.
2. to simulate the designed pipelined datapath and control on the stimulus file testfixture1.new.
3. to modify the stimulus file testfixture2.new used in Lab 4 and then simulate the designed pipelined CPU on the modified stimulus file. Since there are many dependencies among the instructions in testfixture2.new, it would cause data hazards in the pipelined CPU. In order to make the pipelined CPU to work properly, you have to insert the nop instructions to legislate data hazards out of existence. The abbreviation nop stands for "no operation," because nop neither modifies data nor write a result. In the next Lab Exercise, you will see hardware schemes for resolving data hazards.
1. The MIPS nop represents sll $0, $0, 0, in the textbook, which shifts the register 0 left 0 places. Although instruction sll  is not implemented in the designed datapath, the instruction sll $0, $0, 0 can be supposed to execute.
4. to write report in English. The report must be typed and include the final schematic of the pipelined datapath and control, the modified stimulus file you created from testfixtures.new2, and simulation results. In case you use Verilog to design IF/ID pipeline register, ID/EX pipeline register, EX/MEM pipeline register, and MEM/WB pipeline register, please include the Verilog codes of four pipeline registers in your report.

  Back to Exercise Page of Computer Architecture Course .