// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus. 

initial
begin 

`define R_TYPE     6'b000000
`define ADDI       6'b001000
`define ANDI       6'b001100
`define ORI        6'b001101
`define LW         6'b100011
`define SW         6'b101011
`define BEQ        6'b000100
`define SLTI       6'b001010
`define J          6'b000010
`define ADD_FUNCT  6'b100000
`define SUB_FUNCT  6'b100010
`define AND_FUNCT  6'b100100
`define OR_FUNCT   6'b100101
`define SLT_FUNCT  6'b101010


//                      instruction codes                       labels  instructions    ; comments

IMem.cell['h0]={`ADDI,   5'd0,  5'd4,  16'd0};                  //       addi $4, $0, 0      ; $4 = 0;
IMem.cell['h4]={`ADDI,   5'd0,  5'd3,  16'd1};                  //       addi $3, $0, 1      ; $3 = 1;
IMem.cell['h8]={`ADDI,   5'd0,  5'd1,  16'd0};                  //       addi $1, $0, 0      ; $1 = 0;
IMem.cell['hc]={`ADDI,   5'd0,  5'd6,  16'd16};                 //       addi $6, $0, 16     ; $6 = 16;

IMem.cell['h10]={`LW,     5'd1,  5'd2,  16'h1000};              //WHILE: lw   $2, 'h1000($1) ; $2 = Mem['h1000 + $1];
IMem.cell['h14]={`R_TYPE, 5'd4,  5'd2,  5'd4, 5'd0, `ADD_FUNCT};//       add  $4, $4, $2     ; $4 = $4 + $2;
IMem.cell['h18]={`ADDI,   5'd1,  5'd1,  16'd4};                 //       addi $1, $1, 4      ; $1 = $1 + 4;
IMem.cell['h1c]={`ADDI,   5'd3,  5'd3,  16'd1};                 //       addi $3, $3, 1      ; $3 = $3 + 1;

IMem.cell['h20]={`R_TYPE, 5'd6,  5'd3,  5'd5, 5'd0, `SLT_FUNCT};//       slt  $5, $6, $3     ; $5 = $6 < $3;
IMem.cell['h24]={`BEQ,    5'd5,  5'd0, 16'hfffa};               //       beq  $5, $0, WHILE  ; if($5==$0) goto WHILE;
IMem.cell['h28]={`SW,     5'd0,  5'd4,  16'h1040};              //       sw   $4, 'h1040($0) ; Mem['h1040] = $4;
IMem.cell['h2c]={`BEQ,    5'd0,  5'd0, 16'hffff};               //WAIT:  beq  $5, $0, WAIT   ; goto WAIT;


Mem.cell['h1000]=8;
Mem.cell['h1004]=4;
Mem.cell['h1008]=7;
Mem.cell['h100c]=12;
Mem.cell['h1010]=13;
Mem.cell['h1014]=19;
Mem.cell['h1018]=23;
Mem.cell['h101c]=43;
Mem.cell['h1020]=56;
Mem.cell['h1024]=32;
Mem.cell['h1028]=41;
Mem.cell['h102c]=4;
Mem.cell['h1030]=56;
Mem.cell['h1034]=7;
Mem.cell['h1038]=5;
Mem.cell['h103c]=66;
Mem.cell['h1040]=0;



   CK = 1'b1;
   CLR = 1'b1;
   #110
   CLR = 1'b0;
   #55000        
   $display("RESULT:");
   $display("Mem.cell['h1040]= %d",Mem.cell['h1040]);
   $finish;
end

always #250 CK=~CK;