FACULTY
Research and Industry-Academia Collaboration
研究・産学連携
SUZUKI Daisuke
Associate Professor
- Affiliation
- Department of Computer Science and Engineering/Division of Computer Engineering
- Title
- Associate Professor
- daisuke@u-aizu.ac.jp
Education
- Courses - Undergraduate
- FU05 Computer Architecture
OT03-026 The Basis of LSI Design Using a Software-Like Hardware "FPGA"
LI13 CSE Exercise I
NS04 Semiconductor Devices
OT03-033 Let's Draw "Micro" Circuits -An Introduction to CMOS Logic Circuit Design-
SY02 Electronics
- Courses - Graduate
Research
- Specialization
-
Electron device and electronic equipment
Computer architecture, Integrated circuits, Reconficurable Systems, Artificial intelligence
- Educational Background, Biography
- Current Research Theme
- 1. Logic circuit design using emerging nonvolatile devices
2. Nonvolatile field-programmable gate array (FPGA)
3. Application of nonvolatile FPGA to edge devices, AI accelerators, etc.
- Key Topic
- Nonvolatile logic, FPGA, AI, Edge computing
- Affiliated Academic Society
- IEICE, IEEE, IPSJ
Others
- Messages for Students
- ・「習うより慣れろ」とよく言いますが，やはりこの分野は理論と演習をセットにして学ぶのが効率がいいと思います。大学の計算機室などを積極的に活用しましょう。
・Linuxの知識はソフト系，ハード系のエンジニア共に役立ちます。最近では仮想マシンもフリーで入手できるので，仮想マシン上でのLinuxを立ち上げるなどトライしてみてください。
Dissertation and Published Works
1. D. Suzuki, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, "Six-input Lookup Table Circuit with 62% Fewer Transistors Using Nonvolatile Logic-in-Memory Architecture with Series/Parallel-Connected Magnetic Tunnel Junctions," Journal of Applied Physics (JAP), vol. 111, issue 7, pp. 07E318~1-07E318~3, Feb. 2012.
2. D. Suzuki, M. Natsui, A. Mochizuki, and T. Hanyu, "Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic," IEEE Trans. Magn., vol. 50, no. 11, pp. 3402104~1-3402104~4, Nov. 2014.
3. M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu, "An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40 nm CMOS/MTJ Hybrid Technology Achieving 47.14 W Operation at 200 MHz," 2019 IEEE International Solid-State Circuits Conference (ISSCC), pp. 202-203, Feb. 2019.