Lecture Datapath

Reading materials of Lecture 7:

1. Chapter 5.1 Introduction in the text book.
2. Chapter 5.2 Building a Datapath in the text book.

Section 1 Review of the Implementation of Instructions

Type 1: Arithmetic-logical instructions (add, sub, and, or, slt),

Step 1: Send PC (program counter) to the instruction memory,
              and fetch an instruction from instruction memory.

Step 2:  Read two registers using the field bits in the instruction to select
              registers to read. Meanwhile, decode the instruction.

Step 3: Use  ALU to execute either arithmetic (+, -) or
              logical operations (AND, OR).

Step 4: write ALU result back to  register.
 
 

Type 2: Data transfer instructions (lw, sw)

Step 2:  Read two registers for sw , and one register for lw
              using field bits in the instruction to select registers to read.
             Meanwhile, decode the instruction.

Step 3: Use  ALU to calculate the address.

Step 4: Use ALU result as address to access
              data memory. For lw, use the address as the read
              address. For sw, use the address as the write address.

              This is the end of execution of sw.

Step 5: For  lw only, write the data from data memory to register file.
             ALU execution.
 

Type 3: Branch instruction (beq)

Step 1: Send PC (program counter) to the instruction memory,
              and fetch an instruction from instruction memory.

Step 2:  Read two registers using field bits in the instruction to select
              registers to read. Meanwhile, decode the instruction.

Step 3:  Use ALU to do the comparison.

Step 4: Use ALU result to make a decision either to go to
             next instruction or the branch target.
 

Section 2 Build a Datapath

There are three devices needed for the instruction fetch:

     1. PC (program counter): It is a 32-bit register. There are
         two ways to build PC, either by Verilog or by Schematic.

     2. Instruction Memory

          Instruction memory is used to hold and supply instructions
          given an address. In the design, we only need read function
          in instruction memory because the datapath does not write
          instructions. Since instruction memory is only for read, we
          treat it as combinational logic although it is a sequential
          element.

      module IMem();
            reg [31:0]  dcell [0: 65535] ;  // 64 K words only
      endmodule

      module instruction_mem(DO, ADR);
           input    [31:0]   ADR;
           output  [31:0]   DO;

            assign #5 DO = IMem.dcell[ADR & 16'hffff];

       endmodule
 

     3. Adder

     Since only one operation in Adder, i.e. addition. It is
     combinational device. Because there is only one operation,
     no control line such as operation needed in ALU. Adder
     is combinational device.

Part 2: datapath for R-format instruction. See Figs 5.6 and 5.7.

     Two devices are needed. They are Register File and ALU.

Part 3: datapath for lw and sw. See Figs 5.8 and 5.9.

     The following devices are needed:
           a.  Register File
           b.  ALU
           c.   Sign-extend unit
           d.   Data Memory

      Verilog of Sign-extend unit:
            module sign_ext(din, dout);
                   input    [15:0]     din;
                   output  [31:0]     dout;

                   assign dout = {{16{din[15]}}, {din[15:0]}};  // replication and concatenation
            endmodule

        Verilog of Data Memory: sequential device. There are two control
              signals WRITE and READ that control READ and WRITE
              operation in Data Memory.

              module Mem();
                   reg [31:0] dcell [0:65535];                     // 64K words
              endmodule

              module mips_mem(DO, ADR, DI, WRITE, READ, CLK);
                  input     [31:0] ADR;
                  input     [31:0] DI;
                  input      WRITE, READ, CLK;
                  output   [31:0] DO;

                  assign #5 DO = (READ == 1)? Mem.dcell[ADR & 16'hffff] : 32'bx;

                   always@(negage CLK)
                        begin
                            if (WRITE == 1) Mem.dcell[ADR & 16'hffff] = DI;
 
             endmodule
 

Part 4: datapath for beg. See Fig 5.10.
 

     The following devices are needed:
           a.  Register File
           b.  ALU
           c.   Sign-extend unit
           d.   Shift left 2 bits
           e.    Adder

      beq $t1, $t2, offset

      if $t1 == $t2, go to the branch target address; else, go to PC + 4.

      How to calculate the branch target address?

           branch target address = (PC + 4) + offset * 4

• (PC + 4) is the base address.
• offset*4 means that the datapath shifts the offset field left 2 bits so that it is a word offset.

            module shift_left)2(din, dout);
                  input   [31:0]  din;
                  output [31:0]  dout;

                  assign dout = {{din{29:0]}, {2'b00}};
            endmodule