Lecture Overview of Single Cycle MIPS Processor

Reading materials of this Lecture:

  1. Chapter 5.2 Introduction in the text book.
  2. Chapter 5.2 Building a Datapath in the text book.
 

We have learned three types of MIPS instructions:

• arithmetic-logical instructions: add, sub, and, or, slt
• data transfer instructions: lw, sw
• branch instruction: beg

Section 1 An Overview of the Implementation

Major steps to execute different instructions:

Step 1: Send PC (program counter) to the instruction memory,
              and fetch an instruction from instruction memory.

Step 2:  Read registers (one or two registers), using fields in
              instructions to select registers to read. Meanwhile,
              decode the instruction.

Step 3:  ALU execution.

     a. For the arithematic-logical instructions, use ALU to do
          some operation, such as +, -, AND,  OR.

     b. For lw and sw, use ALU to calculate the address.

     c. For branch beg, use ALU to do the comparison.

Step 4: All instructions use the ALU results.

     a. For the arithematic-logical instructions, write ALU
          result back to register.

     b. For lw and sw, use ALU result as address to access
          data memory. For lw, use the address as the read
          address. For sw, use the address as the write address.

     c. For branch beg, use ALU result to make a decision
         either to go to next instruction or the branch target.

The above steps are clearly shown in the Fig 5.1.

Section 2 Build a Datapath

There are four devices needed for the instruction fetch

   1. PC (program counter):

        It is a 32-bit register. There are two ways to build PC,
        either by Verilog or by Schematic.

   2. Instruction Memory

        Instruction memory is the place to store the instructions. In our
        design, the instruction memory need only provide READ access
        because the datapath does not write instructions. Since the instruction
        memory is only for read, it can be treated as COMBINATIONAL
        DEVICE.

        module IMem();
              reg [31:0] icell [0:65535];                     // 64K words
        endmodule

        module instr_mem(DO, ADR);
              input     [31:0] ADR;
              output   [31:0] DO;

              assign #5 DO = IMem.icell[ADR & 16'hffff];  // only lower 16 bits are
                                                                                                // used as address
         endmodule

   3. Adder

       It is a combinational device. Since only one operation in Adder,
        i.e. addition, the control line operation in ALU is not needed
        in Adder.