1. Signal in Verilog
a. net -- represent physical connections between hardware elements.
No any storage capacity.
Values of net is determined by
(1) values of signal sources
(2) high-impedance when the net is not connected
to any driver.
b. register-- able to store values. Even when disconnected, assigned
values
are kept until a new value is assigned.
binary signal values: 0, 1 , x (unknown), z (high impedance)
The default value of a net is high-impedance (z), and the default value
of
register is unknown value (x).
Example:
At the beginning, no any source is connected to net and register:
-------------
----| net | ----- z
| -------------
----- |
| -------------
----| register | ----- x
-------------
Then, source 0 is connected to both net and register:
-------------
----| net | ----- 0
| -------------
0 ----- |
| -------------
----| register | ----- 0
-------------
After that, source 0 is disconnected:
-------------
----| net | ----- z
| -------------
----- |
| -------------
----| register | ----- 0
-------------
The main difference between nets and registers can be observed when
they are disconnected from source. Nets will switch to high impedance,
while registers preserve their previous values.
2. Scalar Signals and Vector
Scalar signals: single line signal
input A; // 1 bit
Vector: multiple-line signals
input [31: 0] A ; // 32 bits
[MSB : LSB], LSB : the least significant bit
MSB : the most significant bit
3. Continuous assignment and procedural assignment
assign Q = D; // continuous assignment
always@(...)
begin
...
end
4. initial process and always process
There are two processes: initial process and always process.
Initial process is only executed once. However, always process
might be executed repeatedly.
initial
begin
...
end
always@(...)
begin
...
end
5. Conditional operator, if-else statement, case statement
a. Conditional operator
assign Y = (S == 2'b00) ? D[0] :
(S == 2'b01) ? D[1] :
(S == 2'b10) ? D[2] :
(S == 2'b11) ? D[3] : 1'bx;
b. if-else statement
if (S == 2'b00)
Y = D[0];
else if (S == 2'b01)
Y = D[1];
else if (S == 2'b10)
Y = D[2];
else if (S == 2'b11)
Y = D[3];
else
Y = 1'bx;
c. case statement
case(S)
2'b00 : Y = D[0];
2'b01 : Y = D[0];
2'b10 : Y = D[0];
2'b11 : Y = D[0];
default: Y = 1'bx;
endcase
Both if-else and case statements cannot be used in the continuous
assignment. They can be used in the process ONLY. However,
conditional operator can be used in both the continuous assignment
and processes.