Lecture 3 Register File and its Design

Reading materials of Lecture 3:

  1. Chapter 5.1 Introduction in the text book.
 

Some questions about ALU Verilog Design:

Two questions are discussed about Verilog Design of ALU:
Question 1: How to reference of bits in a vector?
       for example:
       output [31:0] result;

       after the declaration, you can reference the whole
       vector either by result or by result[31:0]. For some
       bits among the vector, result[4:0] represents the
       lowest 5 bits, result[31:28] are the highest 4 bits.

Question 2: How to compare two signed value?
It is often to represent the signed values by the two's
complement. For example, a = 1, b= -1, if represented
in 32-bit in the two's complement, they will be

  a= 0000 0000 0000 0000 0000 0000 0000 0001

  b= 1111 1111 1111 1111 1111 1111 1111 1111

If use the compare operators, such as ">", since
Verilog treats values as unsigned values, the statement

if (a < b) result = 1;
else result = 0;

would  tell "a < b"  is true, in another word,  it means
1 < -1. It is certainly not correct if we think a and b as
signed value.

How to make a correct comparison?

   a < b  <===> a - b < 0

From the result of (a - b), we can tell whether a < b or not.
 

Section 1 Schematic Design of Register File

Section 2 Verilog Design of Register File

Example 1: 1-bit D flip-flop with a falling edge

    module DFF_falling(data, clk, clear, q);
         input data;
         input clk;
         input clear;
         output q;
         reg  q;

        always@(negedge clk or posedge clear)
             if (clear)
                 q = 1'b0;
             else
                 q = data;

    endmodule

In Example 1, we use an edge-triggered design, i.e., either the rising
edge or falling edge of the clock is active, and causes the state to be changed.

Clock is simply a free-running signal with a fixed cycle time. It
oscillates between high and low values:

                   high
             ----------              ----------
_____  |                          |______|                          |_____
            rising edge             low                            falling edge
 
There are two operations in Register File:
     read: it is not clocked, and combinational.  Given the same
               input, a combinational circuit always produces the same output.

     write: it is clocked, and it is sequential. A sequential circuit depends
                on both inputs and internal states. An circuit contains state
                if it has some internal storage.

After declare an array of vectors
      reg [31:0] register[31:0]
we have 32 32-bit registers.

For read operation:
      assign #5 read1 = register[readreg1];
      assign #5 read2 = register[readreg2];

#5 is a time delay. readreg1 is 5-bit address index for 32 registers.

For write operation,
     always@(negedge clock or posedge clear)
          if (clear == 1)
              clear the signals
          else
              write to registers

How to clear the signals:
 
         for(i = 0;  i<32;  i=i+1)
              register[i] <= 0;

How to write to registers:

        if (RegWrite)
           begin
              register[writereg] = data;    // write
              register[0] = 0;                       // write 0 back to register zero as precaution.
           end