Lecture A Pipelined Datapath

Reading materials of this Lecture:

Chapter 6.1 An Overview of Pipelining in the text book
Chapter 6.2 A Pipelined Datapath in the text book.

Section 1 Pipelined Datapath

Fig.6.3 shows single-cycle non-pipelined execution in top vs.
pipelined execution in bottom.

Based on the execution steps used by instructions, we could divide
the datapath in to five stages.

Five-stage pipelined datapath shown in Fig. 6.10 in the text book:
1. IF       : Instruction fetch
2. ID      : Instruction decode and register file read
3. EX     : ALU execution
4. MEM: Data memory access
5. WB   : Write back.

Since at most five instructions can be in the datapath at
the same time for five-satge datapath, we need to save information
needed by each instructions. For example, if we did not save one
instruction bits, the following instruction entering the datapath
will re-write the previous instruction. All the information for
the previous one will be lost.

Similar to that PC (program counter) passes the instruction
address from one clock cycle to the next clock cycle, we can
insert registers between two stages, shown in Fig. 6.12 in the text book.

IF/ID registers: PC address, instruction

ID/EX registers: PC address, Read Data 1, Read Data 2, sign-extended offset

EX/MEM registers: branch address, Zero signal, ALU result, Read Data 2

MEM/WB registers: Read Data from Data Memory, ALU result

Section 2 Examples of the Five Stages of Pipelined Execution

Example 1: lw instruction. See Figs. 6.13, 6.14, and 6.15

Stage 1 (IF) : instruction is read from Instruction Memory using
the address in the PC, and then saved in the IF/ID pipeline register

read save
PC --> Instruction Mem --> instruction --> IF/ID register

4 save
PC--> incremented PC --> IF/ID register

Stage 2 (ID) :

Stage 3 (EX) :

Stage 4 (MEM) :

read read save
EX/MEM --> address --> Data Mem --> data --> MEM/WB

Stage 5 (WB) :

read write
MEM/WB --> dada ----> Register File

Example 2: sw instruction. See Figs. 6.16, and 6.17

Stage 1 (IF) : instruction is read from Instruction Memory using
the address in the PC, and then saved in the IF/ID pipeline register

read save
PC --> Instruction Mem --> instruction --> IF/ID register

4 save
PC--> incremented PC --> IF/ID register

Stage 2 (ID) :

Stage 1 and Stage 2 are executed by all instructions since it is too early
to know the type of instructions.

Stage 3 (EX) :

                                       read
                                     |---> Read data 1 ------->|
ID/EXE register ->| read                                                |->ALU -> address ->EX/MEM
                                     |--> sign-extended 32-bits ->|
                                     |
                                     | --->Read data 2------------------------>EX/MEM

Stage 4 (MEM) :

                    read
EX/MEM -->|---> address
                            |                                    write
                            |---> Read data 2 ---> Data Mem

Stage 5 (WB) : Nothing happens.

An instruction passes through a stage even if there is nothing to do because later
instructions are already in progress.

What is the correct Write Register needed in the Stage WB?

In Fig. 6.15, the Write Register needed in the Stage WB is from
pipeline register IF/ID. However, the bits of Write Register
are from an instruction in the Stage ID. In another word,
lw instruction in the Stage WB uses Write register in another instruction
in the Stage ID. It leads to write the data to a wrong destination register
in Register File. In order to have the correct the Write Register, we need
to save the information of 5-bit destination register through ID/EX,
EX/MEM, and MEM/WB, see Fig. 6.18.

Section 3 Pipeline Diagrams

Two basic styles of pipeline figures:

multiple-clock-cycle pipeline diagrams : shows the complete execution of instructions in a single figure. Instruction order is from top to bottom, and clock cycles move from left to right.
single-clock-cycle pipeline : show the every detail and the state of the entire datapath during a single datapath.

Example : lw $10, 20($1)
sub $11, $2, $3

Fig. 6.20 shows the multiple-clock-cycle pipeline diagram of two instructions.

Figs 6.22, 6.23. 6.24 shows the single-clock-cycle pipeline diagrams of two instructions in the different clocks.