Lecture 1 Course Introduction and Overview of Verilog

Part 1: Course Introduction :

1. Instructors :

   Contact address:

        Prof. Chu : w-chu@u-aizu.ac.jp

        Prof. Liu : yliu@u-aizu.ac.jp
                           office  102B

        If you have any questions or suggestions, please write to us. You also  can drop in
        my office to talk with me  on anything concerning about the course.
 
 

2. Text Book:

                   The Japanese translation of the book is also available. The
                   information can be found at:
                   http://bpstore.nikkeibp.co.jp/item/main/148222805780.html

                  You can use either English text book or the Japanese text book.
 

3. Course Description:

  1. A tutorial introduction to Verilog hardware description language
  2. Review of MIPS assembly language
  3. Datapath and Control
        (1) A single-cycle implementation
        (2) A multicycle implementation
  4. Enhancing performance with pipelining
        (1) Pipelined datapath
        (2) Pipelined control
        (3) Data hazards and forwarding
        (4) Data hazards and stalls

4. Course Objectives:

      (2)  to learn design of the MIPS processor from a simple implementation to a
              fully pipelined version

      (3)  to learn how to evaluate the performance of the design

      (4)  to introduce Verilog hardware description language for digital computer
            design
 
 

5. Student Evaluation

     Class participation:

           I quoted the above words from the Student Affairs Section. According to
           the rule, you have to attend the AT LEAST 9 classes for  Lectures
           and 18 for Exercises. If you failed on attending the required the number of classes,
           you need to give me a report to state the reason why you cannot do it.
           If your attendance is less than 9 (< 9) for  Lecture and 18 for Exercise,
           you will lose the right to take the examination of this course.
 

       Lab Exercise:

            Please do your exercise design by yourself. You can ask helps from
            professors or Teaching Assistants or your classmates. However, you
            CANNOT copy other students' file or design work. If such thing happens,
            all students involving in it will be severely punished for their final marks.

        Final Exams:

6. Course Web Page

            http://www.u-aizu.ac.jp/~yliu/teaching/comparch/syll.html

     If you want to get the lecture notes, go to

            http://www.u-aizu.ac.jp/~yliu/teaching/comparch/lecture.html

     If you want to find the course information of Computer Architecture Exercise, go to

            http://www.u-aizu.ac.jp/~yliu/teaching/comparch/exe.html
 
 

Part 2 Overview of Verilog

     Verilog is hardware description language (HDL) used for describing and designing
     hardware.

     You can find Verilog Backgrounder from the link

     http://www.doulos.com/knowhow/verilog_designers_guide/

     In this course, we only learn part of Verilog HDL that is needed for our design task. You will learn Verilog by example and by design.

     Verilog can give make descriptions and design in different levels. We will introduce three types of Verilog codes:
        (1) Structural Description: equivalent to schematic
        (2) Dataflow Description:   use the assignment statements based on Boolean equations
        (3) Behavioral Description: description at a level higher than the logic level
 

       Example 1: Structural Verilog for 2-to-1 Multiplexor

        module   multiplexor_2_to_1_str(d,a,b,c);      // module declaration
            input        d, a, b;                                               // input declaration
            output      c;                                                       // output declaration

            wire        not_d;                                              // wire is the default net type
            wire          N_a, N_b;

            not     (not_d, d);                                            // primitive not gate

            and    (N_a, not_d, a);                                  // primitive and gate
            and    (N_b, d, b);

            or       (c, N_a, N_b);                                      // primitive or gate

       endmodule                                                      // ending by endmodule, no semicolon (;)
 

Example 2: Dataflow Verilog for 2-to-1 Multiplexor

        module     multiplexor_2_to_1_df(d,a,b,c); // module declaration
            input     d, a, b;                                              // input declaration
            output   c;                                                      // output declaration

            assign    c = (~d & a) | (d & b);                //  assignment using bitwise operation
                                                                                     // ~   bitwise NOT operation
                                                                                    //   & bitwise AND operation
                                                                                     //   |   bitwise  OR    operation
       endmodule                                                      // ending by endmodule, no semicolon (;)

Example 3: Behavioral Verilog for 2-to-1 Multiplexor

        module     multiplexor_2_to_1_beh(d,a,b,c); // module declaration
            input      d, a, b;                                              // input declaration
            output    c;                                                      // output declaration
             reg         c;

             always@ (d or a or b)                                    // always statement. Whenever the events in the list
                                                                                    //  change, the statement will be executed. For example,
                                                                                    //  if the input a change the value from 0 to 1
                      case (d)                                                //  case statement, very similar to the switch in C language
                         1'b0 :  c = a;
                         1'b1 :  c = b;
                   endcase                                             // case statement start with case and end with endcase

       endmodule                                                      // ending by endmodule, no semicolon (;)
 

All red color words in the  examples, such as module and input, are keywords in Verilog.