Verilog Design of a 32-bit ALU

ALU Specification: A 32-bit ALU that performs AND, OR, addition, subtract, and set on less than. The 32-bit ALU is shown in the figure. In your design, output Overflow will not be considered. For the detail description, please read Section 4.5 in the text book. The values of the three ALU control lines Bnegate (Binvert and Carryln) and Operation and the corresponding ALU operation are shown in the following table.

For the set on less than operation, the result of ALU is 1 if a < b, and 0 otherwise. 

Lab Requirements:

1. to get familiar with Verilog design using Cadence, Prof. Chu provided the help for your first erercise. The working steps for Verilog desing are listed in Help of Lab 1. For more details about Cadence version 4.4.5, go to User's Guide to Cadence version 4.4.5 or online help.
   
2. to get familiar with Verilog language, you could study the following codes for a 32-bit ALU (see the figure 1 and figure 2) that performs AND, OR, and addition. The code alu3.v gives higher level behavioral descriptions of the ALU. It uses case statement. Later you will learn to use other statements to do the same design.
3. to use Verilog (either structural description or behavioral description) to design a 32-bit ALU that performs AND, OR, addition, subtract, and set on less than operations described in the ALU Specification. Hints:
• modify the code alu3.v to add subtract and set on less than operations.
• for the set on less than operation on a and b, the result of ALU depends on the sign bit of (a-b), i.e., the highest bit of (a-b).
4. to debug the code and test the designed ALU on the cases given in the following tables. Hints for Verilog code simulation:
• When there are no bugs in the Verilog code, save it and then open it in read-only.
• In the window of Verilog-Editor Editing, select Verilog-XL from Tools. The following steps are the same as those in schematic simulation.
• After the successful simulation, create the symbol of your designed ALU. You need include ALU symbol in your later CPU design.
5. to write report in English. The report must be typed and include the Verilog code with short comments and simulation results. In your report, you should explain why result of comparison (D8A3 B8D3  < 63B9 D6F2) is 0 rather than 1. Note D8A3 B8D3 is negative.

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