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2023”N3ŒŽ CŽm‘²
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Mask Optimization Methods for Improvement of Quality and Execution Time by Guided Local Search
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Development of Human Detection System With Low Power Consumption Using Sensors in Smart Museum
2023”N3ŒŽ Šw•”‘²
–ī–ģ —I¶
Method of Merging Net Pairs Considering Critical Path Delay in Approximate Computing
‘qŽ ‹§Šó
Construction of Lithography Simulation Environment in Various Optical Conditions and Mask Optimization
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Monte Carlo Tree Search for Maximum Independent Set Problem
2022”N3ŒŽ Šw•”‘²
‘ŠąV •ü‰p
Improvement of Design Flow in Approximate Computing for Large-Scale Circuits
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Tuning Range Optimization Method for Performance Improvement on Post-Silicon Delay Tuning
’†ŽR °‹M
Study on Suitable Hardware and Algorithm for Combinatorial Optimization Problems
2021”N3ŒŽ Šw•”‘²
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Clock Circuit Optimization Method for Performatnce Improvement on Post-Silicon Delay Tuning
–ģč T“ń
Layout Design Flow for Performance Improvement by Placement Compaction in Approximate Computing
–ģ’† ®‹M
Acceleration of Process Variation-aware Mask Correction Method Using Pixel Fixing
2020”N3ŒŽ CŽm‘²
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Process Variation-aware Mask Optimization with Iterative Improvement using Subgradient Method
Žŗˆä F‘¾
Design Flow for Power Consumption Reduction and Yield Improvement on Post-Silicon Delay Turning
Š±ź Ž÷
Analytical Placement Considering Routing Congestion by Quasi-Newton Method
2020”N3ŒŽ Šw•”‘²
›–ģ ‹MO
Improvement of Layout Design Method Using Multiple Supply Voltages in General-Synchronous Framework
ūü‹“ Œõ‹K
Power Consumption Reduction of Arduino Compatible Board Using I2C Equipment by DVFS
‰H“c ŠģŒõ
Circuit Design Method Using Approximate Computing
2019”N3ŒŽ CŽm‘²
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Layout Design Method for Low Power in General-synchronous Framework Using Multiple Supply Voltages
2019”N3ŒŽ Šw•”‘²
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Power Consumption Reduction of Arduino Compatible Board by DVFS
ŽR’† ‘åō
FPGA Implementation of AVR Compatible Processor in General-Synchronous Framework
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Maximum Wire Length Routing Algorithm by Upper Bound Estimation on PCB
2018”N3ŒŽ CŽm‘²
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Analytical Pacement Using SPICE Simulator in LSI Circuits
2018”N3ŒŽ Šw•”‘²
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Pixel-based OPC using Quadratic Programming for Mask Optimization
Žŗˆä F‘¾
Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning
Š±ź Ž÷
Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
“‚‹“ ‰Ā“Ž
Implementation of AVR Compatible Processor into FPGA in General-Synchronous Framework
2017”N3ŒŽ ”ŽŽm‘²
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Digital LSI Design Methods Considering Process Variations in Advanced Technology Nodes
2017”N3ŒŽ CŽm‘²
Ž›“c –œ—
Implementation Flow in General-Synchronous Framework using Engineering Change Order for Xilinx FPGA
2017”N3ŒŽ Šw•”‘²
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Design Method using Multiple Supply Voltages for Low Power in General-Synchronous Framework
2016”N3ŒŽ CŽm‘²
‘åź ‘ō–ē
Implementation of General-synchronous Circuits into Altera FPGA using Prescribed-Domain Clock Skew Scheduling
2016”N3ŒŽ Šw•”‘²
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Analytical Placement Using SPICE Simulator in LSI Circuits
2015”N3ŒŽ CŽm‘²
–{‘½ FL
Acceleration for Any-Angle Routing using Quasi-Newton Method on GPGPU
ģŒū ƒŽ÷
Technology Mapping Method for Low Power Consumption in General-Synchronous Framework
2015”N3ŒŽ Šw•”‘²
Ž›“c –œ—
Iterative Improvement Method for Peak Power Reduction using Multi-Clustering Method in General-Synchronous Framework
“ą“c Wˆź
Improvement of Design Flow for FPGA Implementation in General-synchronous Framework
ą_’J Œ\•ć
Enhancement of Routing Method using Quasi-Newton Method
2014”N3ŒŽ CŽm‘²
ŒKŒ“ ćđ¾
Analytical Placement using Quasi-Newton Method and Acceleration by GPGPU
‘Žq x
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
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Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling
2014”N3ŒŽ Šw•”‘²
āV“” Œ\‰ī
Double Patterning Lithography Layout Decomposition Considering Balance
‘O“c —Eģ
Iterative Improvement Method for Peak Power Reduction using 2-clustering in General-Synchronous Framework
‘åź ‘ō–ē
Layout Design of General-Synchronous Circuits by Current CAD Tools
2013”N3ŒŽ Šw•”‘²
ģŒū ƒŽ÷
Technology Mapping for Low Power Consumption in General-Synchronous Framework
‹v•Ä Ė”V
Peak Power Reduction using 2-Clustering Method in General-Synchronous Framework
ŽRč _Ž”
A Study of Longest Path Problem for a Differential Pair Net
2012”N3ŒŽ Šw•”‘²
ŒKŒ“ ćđ¾
An Effective Overlap Removable Objective for Analytical Placement
ŒĆŽR Ė•½
A Length-Matching Routing Algorithm on Single Layer using Longer Path Algorithm for Single Net
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Acceleration of Parallel Maze-Routing Algorithm Using GPGPU
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Timing Recovery Method for LSI Circuits with Programmable Delay Element