Q1, 2022

Announcement

Instructors
  • Ben Abdallah Abderazek (Lectures @ LTh & Exercises @ HDW1), Email: benab, office 202-A
  • Naohito Nakasato (Exercises @ HDW2), Email: nakasato
TAs
  • HDW1: m5251136 OKADA Yuki ; m5251101 AOYAMA Naoki; m5251138 Sinchhean Phea; m5261153  SAIKAWA Yamato 
  • HDW2: TBD
Classroom
  • Lectures: LTh, Tuesday & Friday (9:00 - 10:40)
  • Exercises: HDW1, HWD2, Tuesday & Friday (10:50 - 12:30)
Course Outline
Students will learn fundamental issues of computer architecture with its design approach, and performance evaluation methods. A computer consists of a central processing unit, memory, I/O devices, and so on. In this course, the students will understand how a computer is established by combining some computing and control units which are composed of logic circuits learned in “Logic Circuit Design” course. More precisely, the students will learn abovementioned issues using MIPS processor as an example. In the exercises, the students will implement a simplified MIPS processor by using CAD (Computer Aided Design) tools such as Cadence. In addition, the students will study how a program runs on a processor through developing some programs using an assembly programming language.
Textbook
- Computer Organization and Design - The Hardware/Software Interface. David. A. Patterson and John L. Hennessy, 5th edition, Morgan Kaufmann Publishers, ISBN 0124077269
Syllabus; Registered Students and ML
Schedule
Date, Period
 Handouts
Reading/Notes
4/08, P1
Lecture 1 Introduction Chapter 1
4/08, P2-P3
Lecture 2 Performance Evaluation  Chapter 1
4/08, P4, 4/12 P1-P2
Lecture 3 Assembly Language I  Chapter 2
4/15, P1-P2
Lecture 4 Assembly Language II  Chapter 2, MIPS ISA subset
4/19, P1-P2 Lecture 5 Arithmetic for Computer I   Chapter 3
4/22, P1-P2,4/26, P1-P2
Lecture 6 Arithmetic for Computer II  Chapter 3
5/6, P1-P2 Lecture 7 Datapath  Chapter 4, Verilog HDL Tutorial
5/10, P1-P2 Lecture 8 Controlpath
Chapter 4
5/13, P1-P2 Lecture 9 Pipeline I Chapter 4
5/17, P1-P2 Lecture 10 Pipeline II  Chapter 4
5/20, P1-P2 Lecture 11 Memory Hierarchy: Cache Chapter 5
5/24, P1-P2 Lecture 12 Memory Hierarchy: Virtual Memory  Chapter 5
5/27, P1-P2 Lecture 13 Storage & other I/Os  Chapter 5
5/31, P1-P2 Lecture 14 Parallel Processor  Chapter 6
6/9 P1-P2
Final Exam (**Only a dictionary is allowed). Rooms: M5 (for HDW1 students) & M6 (for HDW2 students)


Exercises

Updated on April 01, 2022

Save