Q1, 2024
Announcement
Instructors
  • Ben Abdallah Abderazek (Lectures @ M6, Exercises @ HDW1), Email: benab, office 202-A
  • Naohito Nakasato (Exercises @ HDW2), Email: nakasato
Classroom
  • Lectures: LTh, Tuesday & Friday (9:00 - 10:40)
  • Exercises: HDW1, HWD2, Tuesday & Friday (10:50 - 12:30)
Course Outline
Students will learn fundamental issues of computer architecture with its design approach, and performance evaluation methods. A computer consists of a central processing unit, memory, I/O devices, and so on. In this course, the students will understand how a computer is established by combining some computing and control units which are composed of logic circuits learned in “Logic Circuit Design” course. More precisely, the students will learn abovementioned issues using MIPS processor as an example. In the exercises, the students will implement a simplified MIPS processor by using CAD (Computer Aided Design) tools such as Cadence. In addition, the students will study how a program runs on a processor through developing some programs using an assembly programming language.
Textbook

- Computer Organization and Design MIPS Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) Paperback – December 4, 2020
- Computer Organization and Design - The Hardware/Software Interface. David. A. Patterson and John L. Hennessy, 5th edition, Morgan Kaufmann Publishers, ISBN 0124077269
Syllabus; Registered Students and ML
Schedule
Date, Period
  Handouts
 Reading/Notes
4/08, P1
 Lecture 1 Introduction Chapter 1
4/08, P2
 Lecture 2 (3) Assembly Language I
Chapter 1
4/11, P1-P2
Lecture 3 (4) Assembly Language II
Chapter 2
4/15, P1-P2
 Lecture 5 Arithmetic for Computer I   Chapter 2, MIPS ISA subset
4/18, P1-P2 Lecture 6 Arithmetic for Computer II Chapter 3
4/22, P1-P2
 Lecture 6 Arithmetic for Computer II (Cont.); Lecture 4 (2) Performance Evaluation
Chapter 3
4/25, P1-P2 Lecture 7 Datapath  Chapter 4, Verilog HDL Tutorial
5/2, P1-P2
Lecture 8 Controlpath
Chapter 4
5/7, 5/9, P1-P2 Lecture 9 Pipeline I Chapter 4
5/13, P1-P2 Lecture 10 Pipeline II  Chapter 4
5/16, P1-P2 Lecture 11 Memory Hierarchy: Cache Chapter 5
5/20, P1-P2 Lecture 12 Memory Hierarchy: Virtual Memory  Chapter 5
5/23, P1-P2 Lecture 13 Parallel Processors
Chapter 5
5/27, P1-P2 Lecture 14 Storage & other I/Os
Chapter 6
6/2 P5-P6
Final Exam (**Only a dictionary is allowed). Rooms: M5 (for HDW1 students) & M6 (for HDW2 students)


Exercises
Updated on April 01, 2025
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