University of Aizu Master’s Student Wins Two Awards at IEICE Technical Committees on VLSI Design Technologies

The award ceremony for the IEICE (The Institute of Electronics, Information and Communication Engineers) Technical Committee on VLSI (very large scale integration) Design Technologies (VLD Technical Committee) (※1) was held at the Satellite Campus Hiroshima on Thursday, December 6th, 2018. At the ceremony, Rina Azuma, a first-year master's student of the LSI Design Laboratory at the University of Aizu(※2), received the Excellent Englith Thesis Student Author Award(※3).

The VLD Technical Committee focuses on the research fields of VLSI design methodology, design automation, and the associated fundamental algorithms and data structures.

The award was given to her based on the quality of the research and her presentation "Pixel-based OPC using Quadratic Programming for Mask Optimization" at the VLD Technical Committee at the Kitakyushu International Conference Center on May 16th, 2018 as well as the quality of the English paper.

She also received the Best Student Poster Award at the same ceremony on December 6th mentioned above for her poster presentation "Process Variation-aware Model-based OPC using 0-1 Quadratic Programming" at the Design Gaia held at the Satellite Campus Hiroshima on December 5th, 2018(※4).

Design Gaia is a technical conference cosponsored by seven IEICE and three IPSJ technical committees which is held in cooperation with two IEEE chapters. The event was attended by 451 people over 3 days.

Her poster presentation was chosen as one of the top three posters among all 41 presentations for the workmanship of her poster, the quality of the research and her explanation of the research, and her precise answers to questions from the attendees.

Both presentations are based on joint research with Toshiba Memory Corporation, Tokyo Institute of Technology, and Senior Associate Professor Yukihide Kohira from the University of Aizu. Her poster presented a technology to improve the accuracy of OPC (optical proximity correction, a technology to improve resolution) in mask design for the photolithography process utilized in the LSI manufacturing.
The method she presented is expected to reduce the frequency of defects caused by LSI manufacturing process variations.

<Comments from Rina Azuma>
I am deeply pleased to receive the VLD Excellent Englith Thesis Student Author Award and the Design Gaia 2018 Best Student Poster Award. I would like to take this opportunity to express my deepest gratitude to Senior Associate Professor Yukihira Kohide who has been empathetically supervising me since when I was still an undergraduate. I am also deeply grateful to Professor Tomomi Matsui and Professor Atsushi Takahashi from the Tokyo Institute of Technology, Dr. Chikaaki Kodama and Shigeki Nojima from Toshiba Memory Corporation, all of whom gave me great support and advice.
I am pleased that my English dissertation I polished and presented at the VLD Technical Committee was recognized. Part of me was anxious about how this research would be evaluated because not many researchers were working on OPC for mask design. Therefore, being awarded in this way for my poster presentation at the Design Gaia 2018 gave me a great confidence to continue my research. I believe that the award will encourage and motivate me to continue this research, present the findings at international conferences and journals, and contribute to the field of LSI.

• ※1 IEICE (The Institute of Electronics, Information and Communication Engineers) Technical Committee on VLSI (very large scale integration) Design Technologies (VLD Technical Committee)
• ※2 LSI Design Laboratory at the University of Aizu
• ※3 Excellent Englith Thesis Student Author Award
• ※4 Design Gaia 2018