English/Japanese
Junji Kitamichi
Education : Ph.D. in Engineering Science, Osaka University
Research Topics:
- Safety Embedded System
- Formal Approach for Circuits Design and Systems Design
- Design Method at System Design Level
- Heuristic Approaches for Combinatorial Optimization Problems
Publications
(1)Journal Paper
[1-1] Teruo Higashino, Junji Kitamichi, Kenichi Taniguchi
Presburger Arithmetic and its Application to Program Developments,”
Conputer Software,Vol.9,No.6,pp.31-39（1992-11）.
[1-2] Kouzou Okano, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi,
Hierarchical Design of Abstract Sequential Machine Style Program and Its Application to Development of Stock Management Program”,
IEICE Transaction D-I ,Vol.J76-D-I,No.7,pp.354-363（1993-07）.
[1-3]Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi, Yuuji Sugiyama,
“Top Down Design Method for Synchronous Sequential Logic Circuits Based on Algebraic Technique,”
IEICE Transaction A,Vol.J77-A, No.3,pp.420-429（1994-03）.
[1-4]Sumio Morioka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi,
“Automatic Verification of Abstract Sequential Machine Style Programs Written in Algebraic Language,”
Journal of Information Processing,Vol.36, No.10,pp.2409-2421（1995-10）.
[1-5]Nobuo Funabiki,Junji Kitamichi,and Seishi Nishikawa,
"A gradual neural network approach for time slot assignment in TDM multicast switching
systems,"
IEICE Transactions on Communications,Vol. E80-B,No.6,pp.939-947（June 1997）.
[1-6]Takashi Takenaka, Junji Kitamichi, Seishi Nichikawa,
“A Formal Method of Proving Invariants for Synchronous Sequential Circuits with Plural Controllers,”
Journal of Information Processing,Vol.39,No.7,pp.2308-2322（1997-07）.
[1-7]Nobuo Funabiki,Junji Kitamichi,and Seishi Nishikawa,
"A massive digital neural network for total coloring problems,"
IEICE Transactions on Fundamentals,Vol. E80-A,No.9,pp.1625-1629（Sep.1997）.
[1-8]Nobuo Funabiki,Junji Kitamichi,and Seishi Nishikawa,
"A digital neural network for multi layer channel routing with crosstalk minimization,"
IEICE Transactions on Fundamentals,Vol. E80-A,No.9,pp.1704-1713（Sep.1997）.
[1-9]Nobuo Funabiki and Junji Kitamichi,
"A Neural-Greedy Combination Algorithm for Board-Level Routing in FPGA-Based Logic
Emulation Systems,"
IEICE Transactions on Fundamentals,Vol.E81-A,No.5,pp.866-872（May 1998）.
[1-10]Nobuo Funabiki,Makiko Yoda,Junji Kitamichi,and Seishi Nishikawa,
"A Gradual Neural Network Approach for FPGA Segmented Channel Routing Problems,"
IEEE Transactions on Systems, Man , and Cybernetics,vol. 29, no. 4, pp. 481-489(1999.8).
[1-11]Nobuo Funabiki and Junji Kitamichi,
"A Gradual Nural-Network Algorithm for Jointly Time-Slot/Code Assignment Problems
in Packet Radio Networks,"
IEEE Transactions on Neural Networks,Vol.9,No.9,pp.1523-1528(Nov. 1998).
[1-12]Nobuo Funabiki,Junji Kitamichi,and Seishi Nishikawa,
"An Evolutionary Neural Network Approach for Module Orientation Problems,"
IEEE Transactions on Systems, Man, and Cybernetics-PART B,Vol.28,No.6,pp.849-855
(1998.12).
[1-13]Hiroyuki Kageyama, Junji Kitamichi, Nobuo Funabiki,
“Operations of Presburger Arithmetic Using BDD-like Data Structures and Circuits Verification with them,”
Journal of Information Processing,Vol.40,No.4,pp. 1578-1586（1999-04）.
[1-14]Takashi Takenaka, Junji Kitamichi, Kenichi Taniguchi,
“A Formal Verification Method of Pipelined Microprocessors with Out-of-order Execution,”
Journal of Information Processing,Vol.40,No.4,pp.1587-1596（1999-04）.
[1-15]Nobuo Finabiki, Junji Kitamichi,
"A Gradual Neural Network Algorithm for Broadcast Scheduling Problems in Packet Radio Networks,"
IEICE Transactions on Fundamentals,Vol.E82-A No.5 pp.815-824(1999.5).
[1-16]Yasuhito Shikata, Nobuo Funabiki, Junji Kitamichi,
“A Proposal of a Greedy-GA Combined Algorithm for Data Transfer Binding Problems
Journal of Information Processing, Vol.J82-A No.7, pp.1074-1082(1999.7).
[1-17]Nobuo Funabiki,and Junji Kitamichi,
"A two-stage discrete optimization method for largest common subgraph problems,"
IEICE Trans. Information Systems, vol. E82-D, no. 8, pp. 1145-1153(1999.8).
[1-18]Athushi Fukada, Takanori Mori, Akio Nakata, Junji Kitamichi, Masahiro Higuchi, Teruo Higashino,
"Conformance Testing for Communication Protocols Modeled as Concurrent DFSMs with Non-observable Non-deterministic Behavior,"
Journal of Information Processing,Vol.42,No.12,pp.3063-13071（2001.12）.
[1-19]Kenji Asano, Junji Kitamichi, Kenichi Kuroda,
"Dynamic Module Library for System Level Modeling and Simulation of Dynamical
Reconfigurable Systems,"
Journal of Computers, Vol.3, Issue 2, pp.55-62, Academy Publisher, Feb. 2008.
[1-20]Yuji NISHIMAKI, Junji KITAMICHI, Toshiaki MIYAZAKI,
"Development of Education-purpose MIPS Processor Simulator System Visualizing
Internal Operation Behavior ,"
IEICE TRANSACTIONS on Information and Systems (Japanese Edition) vol.J96-D No.10,pp.2130-2138,Oct.,2013.
(2)International Conferences
[2-1]Teruo Higashino,Keiichi Yasumoto,Junji Kitamichi,and Kenichi Taniguchi,
"Hardware Synthesis from a Restricted Class of LOTOS Expressions,"
Proceedings of the 14th International Symposium on Protocol Specification,Testing,
and Verification（PSTV-XIV）,pp.379-386（June 1994）.
[2-2]Junji Kitamichi,Sumio Morioka,Teruo Higashino,and Kenichi Taniguchi,
"Automatic Correctness Proof of Implementation of Synchronous Sequential Circuits Using Algebraic Approach,"
Proceedings of the Second International Conference on Theorem Provers in Circuit Design
（TPCD'94）,Vol.901 of Lecture Notes in Computer Science,pp.165-184（Sep.1994）.
[2-3]Junji Kitamichi,Nobuo Funabiki,and Seishi Nishikawa,
"Proposal of Data Structure for Presburger Arithmetic and its Application to Circuits
Verification,"
Proceedings of 1997 International Symposium on Nonlinear Theory and its Applications,
Vol.2,pp.1233-1236（Nov.1997）.
[2-4]Nobuo Funabiki,Makiko Yoda,Junji Kitamichi,and Seishi Nishikawa,
"A gradual neural network algorithm for FPGA segmented channel routing,"
Proceedings of 1997 International Symposium on Nonlinear Theory and its Applications,
pp.241-244（Nov.1997）.
[2-5]Nobuo Funabiki,and Junji Kitamichi,
"A Three-Stage Greedy and Neural-Network Approach for the Subgraph Isomorphism
Problem,"
IEEE International Conference on Systems, Man , and Cybernetics.pp.1892-1897(Oct. 1998).
[2-6]Junji Kitamichi,Hiroyuki Kageyama,and Nobuo Funabiki：
"Formal Verification Method for Combinatorial Circuits at High Level Design,"
Proceedings of Asia and South Pacific Design Automation Conference1999,pp.177-180
（Jan.1999）.
[2-7]Takashi Takenaka,Junji Kitamichi,Teruo Higashino,and Kenichi Taniguchi：
"Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution,"
Proceedings of Asia and South Pacific Design Automation Conference1999,pp.319-322
（Jan.1999）.
[2-8]Atsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino and Ana Cavalli:
"A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs -Treatment of Non-observable Non-determinism",
Proceedings of 15th International Conference on Information Networking (ICOIN-15), pp.155-162 (Jan. 2001).
[2-9]Hiroaki Tanba, Yasuhiro Yamada, Junji Kitamichi, and Kenichi Kuroda:
“Hardware Implementations of High-Speed Network Monitors ,”
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test,
pp.33-36 (April 2005).
[2-10]Toshiyuki Ito, Junji Kitamichi, and Kenichi Kuroda:
“A Master-Slave Adaptive Load Distribution Processor Model on PCA,”
The 12th Reconfigurable Architectures Workshop(April 2005).
[2-11]Kenji Asano, Junji Kitamichi, and Kenichi Kuroda:
“Proposal of Dynamic Module Library for System Level Modeling and Simulation of
Dynamical Reconfigurable Systems,”
20th International Conference on VLSI DESIGN(VLSID'07),pp. 373-378(Jan. 2007).
[2-12]Shuichi Watanabe, Junji Kitamichi, and Kenichi Kuroda:
“A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem,"
17th International Conference on Field Programmable Logic and Applications(FPL 2007),pp.137-144(Aug. 2007).
[2-13]Junji Kitamichi, Koji Ueda, and Kenichi Kuroda:
“A Modeling of a Dynamically Reconfigurable Processor using SystemC,”
21st International Conference on VLSI DESIGN 2008(VLSID'08),pp.91-96(Jan. 2008).
[2-14]Takahiro Machino, Shin-ya Iwazaki, Yuichi Okuyama, Junji Kitamichi, Ken-ichi Kuroda, and Ryuichi Oka,
"Optimizing Two-Dimensional Continuous Dynamic Programming for Cell Broadband Engine Processors,"
Japan-China Joint Workshop on Frontier of Computer Science and Technology (FCST) 2008, pp.186-193(Dec. 2008).
[2-15]Junji Kitamichi,
"Proposal of Instruction Level Modeling for Dynamically Reconfigurable Processor using SystemC"
17th IFIP/IEEE International Conference On Very Large Scle Integration(VLSI-SOC 2009),(Oct. 2009).
[2-16]Yasue Nagumo, Junji Kitamichi and Kenichi Kuroda,
"Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-
Core Processors using a Reconfigurable Device,"
18th IP-Embedded Systems Conference(IP - ESC 2009),Dec. 2009.
[2-17]Kazunori Nemoto and Junji Kitamichi,
"Improvement of Accuracy and Processing Speed of a Maximum Neural Network
Algorithm for a Channel Assignment Problem,"
2010 International Symposium on Nonlinear Theory and its Applications(NOLTA2010), Sept. 2010.
[2-18]Syuhei Igari, Junji Kitamichi, Yuichi Okuyama and Kenichi Kuroda,
"Proposal of a Dynamically Reconfigurable Processor Architecture with
Multi-Accelerator ,"
IP-Embedded System Conference & Exhibition(IP-SOC2011),Dec.,2011.
[2-19]Shuta Yamamoto, Junji Kitamichi,
A Combinatorial Algorithm of Ant Colony Optimization and Neural Network"
Algorithm for Channel Assignment Problem,"
2013 International Symposium on Nonlinear Theory and its Applications (NOLTA2013), Sep.,2013.
(3)Others
(3-1)Domestic Conference 12
(3-2)Domestic Society 82
Related links
kitamiti@u-aizu.ac.jp