Syllabus
Lecture
Notes
Lab
Exercise
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Computer Architecture
Course
Objectives:
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To expose students to the important principles of computer organization
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To learn design of the MIPS processor from a simple implementation to a
fully pipelined version
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To introduce Verilog hardware description language for digital computer
design
Prerequisites:
Logic Design
Text:
Computer Organization and Design - The
Hardware/Software Interface.
David. A. Patterson and John L. Hennessy, 2nd edition, Morgan Kaufmann
Publishers, ISBN 1-55860-428-6 (cloth). --- ISBN 1-55860-491-X (paper).
The Japanese translation of the book is also available. The
information
can be found at: http://ec.nikkeibp.co.jp/item/books/82660.html
Instructors:
Yong Liu and Wanming Chu
Time/Place:
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Lecture:Fri-3/M1 (Liu)
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Exercises: Fri-4 and Fri-5/hdw1 (Liu) and
hdw2 (Chu)
Course Topics:
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A tutorial introduction to Verilog HDL
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Review of MIPS assembly language
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Datapath and Control
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A single-cycle implementation
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A multicycle implementation
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Enhancing performance with pipelining
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Pipelined datapath
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Pipelined control
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Data hazards and forwarding
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Data hazards and stalls
Student
Evaluation:
Final examination (50), and laboratories reports (50). The
laboratories
reports consist of a number of projects. Students will learn both
schematic
design and Verilog design by doing design in the exercises. Students
are
expected to design the single-cycle datapath and control, and evolve
this
design into a pipelined organization.
The exam will be open book and open notes. There will be a
number of
questions. Some of them may have multiple parts.
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